Verilog Preprocessor (VPP)

Verilog Preprocessor (VPP) is a tool for disciplined preprocessing of Verilog hardware descriptions. Given a description, VPP does pre-expansion static checking, guaranteeing that expansion will produce a well-typed term if the original description is well-typed. In this case, the tool proceeds to the main preprocessing step which is hygienic expansion. During that phase an equivalent description that is free from parameters and iterative constructs is produced. Being free from the mentioned abstractions, the produced description is trivially synthesizable. To achieve its goal, VPP is required to perform iterations and actually evaluate several expressions at expansion time.

Distribution

• Download distribution. This is a prototype version has been tested on Linux and Mac OS X 10.4.

Documentation

• A user guide including installation instructions is now available.
• Download Technical Report.